Understanding capacitance in oscilloscope probe tip
The capacitance in parallel with the 9 megohm resistor is the primary factor in determining the probe capacitance presented to the circuit being probed since, by design, most of the signal voltage (90%) appears across it. At low frequencies, the attenuation of the probe is due to the resistors. At high frequencies, however, the reactance of the capacitors becomes dominant. Then the attenuation of the probe depends on the ratio of the capacitors. For this reason, an adjustable capacitor (usually designated as the compensating capacitor) is included within the probe. By adjusting it, the total capacitance of the oscilloscope input capacitor and the compensating capacitor can be made equal to 9 times the probe capacitance. Thus these capacitors would form a 10:1 voltage divider. In this way, the overall probe and oscilloscope input behave as a 10:1 divider over the full bandwidth of the probe. Another way of looking at it is that the idea is to make the time constant of the 9 megohm resistor and probe capacitance be equal to the time constant of the oscilloscope input (including the compensation capacitor). If that is true, the attenuation of the total circuit will be independent of frequency.
C1 is in series with the input capacitance Cin in parallel with the compensation capacitance C2.
So \$C_{probe}= \frac{1}{\frac{1}{C_1}+\frac{1}{C_2+C_{IN}}}\$
That capacitance is effectively in parallel with 10M when the probe compensation is properly adjusted.
Typically on a garden-variety 10:1 probe, C1 is 10pF, and C2+Cin is about 90pF (when properly adjusted). It's properly adjusted when 1/C1 = 1/(C2+Cin) which makes the divider ratio frequency independent.
C2 includes the cable capacitance as well as the trimcap.
So the probe tip looks like 10M in parallel with 9pF to ground. Since there's a bit of stray capacitance on the input, in addition to C1 there will be a bit more than 9pF capacitance to ground.
The circuit used in real probes is a bit more complex usually, but the above is the basic idea.
When you're measuring a signal, the probe tip loads the circuit, particularly at high frequencies. If the probe tip looks like 10pF, when measuring a 200MHz sine wave, the impedance of the probe is about 80 ohms, which is rather low. Sharp edges such as logic transitions will be rounded a bit as a result, but 10pF is maybe 20% of the test load capacitance of typical 3.3V logic so it's not necessarily a huge effect, and datasheet tr/tf limits will usually still apply.
A typical 10Mohm probe is 9.5 pF which is mostly due to C1 in series with a much larger C of coax and trimcap combined. This results in an input impedance (s11) that drops below 10MOhms with rising frequency due to C1 above 1kHz while the R1C1=T1 =R2C2=T2 to obtain the 10:1 ratio.
Thus the coax and C2 compensation with scope input C combined is about 9x the C1 value.
The scope probes use special high impedance coax to reduce the pF/m in the 100 Ohm region and thus reduce the probe tip compensation C2 and thus C1 input capacitance.
High speed signals must be low impedance to be captured properly by passive probe with no tip and GND clip but the bandwidth is equalized (flattened) by the C2 calibration of the square edge test signal pulse by matching T1=T2.
Don’t forget the 0.5nH /mm added by the ground clip which must be removed to get the maximum bandwidth of the probe. This reacts with the coax capacitance to produce the classic ringing observed by new users of logic high speed signals when longish >1cm ground clips are used and thus causes a resonance above 20MHz. This can also be eliminated by enabling the 20MHz Scope BW option to suppress the inductive ground ringing.
Modern Tektronix passive probes are 40:1 with 250k scope input R to achieve wider flat bandwidth and C1 values of 3.5 pF.
The typical 5V CMOS 74HCxx impedance is in the region of 50 to 66 Ohms with a wider tolerance when loaded by a 9.5 pF probe has an RC time constant defined by the exponential 64% of the step voltage. But in terms of the standard 10~90% rise time, the BW(-3dB)=0.35/Tr.
Tau=RC = 66Ω*9.5pF =627 ps implies a -3dB bandwidth slightly greater than 74HC CMOS so the effects are minimal but still exist on reducing slew rate with C1 load.