Why is propagation delay a function of supply voltage?

I didn't really buy this argument. All else being equal, simply increasing the supply voltage should not increase the small-signal gain, which is out of scope anyways since the 'amplifier' is being over-driven with digital signals.

It really does. Don't think in terms of voltage gain, think in terms of output current:

When you increase the supply voltage, the gate capacitance of a FET is charged quicker, because exponentially more current flows through the involved semiconductor junctions.

That leads to a quasi linear increase of maximum switching speed in modern CMOS ICs. Sadly, you buy that with a raising energy dissipation per switching (=heat!), and thus typically in a superquadratically effort needed to keep the IC at acceptable temperatures. That's one of the main reasons (if not the main reason) there's little complex logic clocked at 10 GHz.

CMOS voltage gain increases with supply voltage due to increased gm. It also reduces RdOn which improves current slew rate into a capacitive load T= Ron*C by increasing peak current and acceleration.

  • what you describe a prop. delay is actually current slew rate.
  • the time to complete a step is due to this slew rate.