Why does ST recommend 100 nF decoupling capacitors for a 72 MHz MCU? (And not 10 nF.)
Three things you should note:
1) Most bypass recommendations in datasheets and application notes are fairly random in my opinion. You may easily be a better engineer than the person who wrote the application note :-). A better datasheet would talk about how low an impedance you as a board designer should provide and to what frequency. I wrote about this here.
2) Most of the parasitic inductance comes from your mounting inductance (footprint and via length) and not the capacitor itself. This is why you would like a smaller package rather than a smaller value. This is also why you would want to get the vias close together and use closely coupled power/ground planes.
3) It's possible that the chip has some bypass as part of the package and die, but this should ideally be detailed in the datasheet before you can take advantage of it (back to my first point). If not (and this is likely), you can try to measure this yourself, like I show here.
You may want to use something like pdntool.com to select the best combination of bypass capacitors based on your impedance and frequency requirements. This method has worked reliably for many projects over the last 15+ years.
I excuse for plugging my own blog posts here, but it's just much faster for me to find the references I need that way. Feel free to ask more questions.
The likely reason , and here I'm making an educated guess - since I did not design that chip, is that ST has incorporated some high quality by-pass caps on chip by using spare area on the die. This capacitance is very high quality, very high resonance and very tiny inductance. What is common is to use the gate, well and even metal layer capacitances, this reduces the off-chip capacitor requirements increasing a customer's likely hood of success.