Why do N-channel MOSFETs have a voltage drop when load is connected on source side?

The difference between the gate voltage and the channel voltage needs to be above the threshold voltage for the MOSFET to conduct well. If the load is between the mosfet and ground, then the more current you push through the mosfet, the more voltage drops over the load and the less gate-source voltage there is.

In the first topology, it doesn't matter how much voltage is dropping across the load, the mosfet always sees Vg - Vs, where Vs is always 0. In the second case, Vs rises with the load current and in turn pinches the mosfet back towards "off". So in the second case, you have Vg - Vs where Vs starts at 0 and increases according to I_load*R_load.

You're effectively lowering Vgs by putting the load below the Nmos.

The reason you are seeing the effect is as follows:

When you put the load between the source and GND then when the N-FET starts to turn on there is voltage drop across the load. This voltage drop is due to the current through the load and the resistance of the load. This voltage drop effectively pushes the source terminal above GND. Pushing the source terminal up like this makes any gate drive be a lower amount by the amount the source is pushed up.

If this effect is pronounced enough it can even tend to begin to take the N-FET out of saturation and start to push it into the linear range. This will result in a greater VDS drop as the channel resistance of the FET rises.