Why are the SRAM data and address pins numbered?
You are quite correct. With an SRAM, where all address pins are equivalent, you can indeed juggle the address pins around within their set on your board to ease layout, and also for the data pins. I would strongly advise putting a note on the board that you've done this, to avoid freaking out any subsequent engineer who comes along to debug or modify it.
Why are they labelled? If the pin functions were labelled 'pool of address pins' and 'pool of data pins', then at some point your CAD tool would insist on identifying them, and you would need to make a choice, even if it was only 'ADR_line_pin_23' sort of identifiers. So they do it for you. It's convenient, and recognisable, each pin has a physical identifier and a function identifier.
When the manufacturer does it, and is consistent with standards like JEDEC, it eases the task of engineers debugging stuff. If I've learned the pinout of a particular package style, then I can expect to find those signals on the same pins without an extra translation step through the schematic, the less mental work I have to do when debugging, the better. 'Let's see, this is word addressable, so the LSB adress shouldn't be changing at all as it reads memory, now where is the LSB'.
Exactly the same goes for multiple functions in a single package. While a quad opamp in a single package tends not to be labelled amp0, amp1 etc, a triple analogue switch does tend to be labelled s0, s1 and s2.
Some reasons :
Pinouts are often standardized between static RAM and EPROM/FLASH: "JEDEC"
RAMs are usually arranged in matrices with lines and columns. Using consecutive addresses may require a little bit less power. For events that affect the matrix, such as hardware defects or a SEU (high energy particle hitting atoms), knowing which memory cells are adjacent may be useful for finding errors or designing error correction codes.
Yes, you can swap address and data pins on static RAM.