What is this operator called as "+:" in verilog

That syntax is called an indexed part-select. The first term is the bit offset and the second term is the width. It allows you to specify a variable for the offset, but the width must be constant.

Example from the SystemVerilog 2012 LRM:

logic [31: 0] a_vect;
logic [0 :31] b_vect;

logic [63: 0] dword;
integer sel;

a_vect[ 0 +: 8] // == a_vect[ 7 : 0]
a_vect[15 -: 8] // == a_vect[15 : 8]
b_vect[ 0 +: 8] // == b_vect[0 : 7]
b_vect[15 -: 8] // == b_vect[8 :15]

dword[8*sel +: 8] // variable part-select with fixed width

Lastly i got the source page for this, this is called as Indexed Vector part Select ("+:").

To explain it a bit more

PQR_AR[44*8 +: 64];

With Indexed vector part select, which is added in Verilog 2000, you can select a part of bus rather then selecting whole bus.

44*8 part is starting point of part select variable and 64 is the width of part select andis constant.It means that if initially we have initialized

input [415:0] PQR;

we are selecting a particular part of PQR using

PQR_AR[44*8 +: 64];

that is PQR_AR[352+:64] or it means that we are taking a part from 352 to 415 out of 0 to 415.