What exactly does ARM sell to vendors?
You're using those terms wrong. "Computer organization" is a rarely-used term for the microarchitecture, and "computer architecture" is a superset of that.
Integrated circuit IP blocks come in two basic forms:
A soft macro is the RTL (VHDL or Verilog) that describes the functional implementation of the IP. This is compiled into a gate-level netlist, which is then turned into a physical layout to produce the mask set for manufacturing. Here's an example from Cadence -- an Ethernet MAC. When you buy it, you get Verilog files, documentation, and a Verilog testbench for verification.
A hard macro is a physical layout of the IP suitable for a given process. It's added to the larger chip layout as a single block, which saves some steps in the design process. Here's another Cadence example -- an Ethernet PHY. It's offered in 180nm and 130nm processes at TSMC, UMC, and SMIC, and is delivered to the customer in the form of GDSII layout files.
ARM sells both of these. The MCUs I've worked on usually use soft macros of ARM Cortex CPUs. We had some older product with ARM7 hard macros, but I don't know if they were hardened by ARM or us. Today, ARM has hard macro versions of the Cortex-A series listed on their web site. Most of their products are synthesizable (soft macros), though. It looks like you can download the (soft) Cortex-M0 for free for non-commercial use on the ARM DesignStart site.
In an SoC, the ARM part is just the CPU. (The designer can also buy peripheral IP from ARM, but it's not required.) The SoCs I've worked on have a mix of third-party and internal IP.
- What exactly is ARM selling to a vendor (eg: freescale)?
A license to sell chips that include ARM intellectual property.
- For a SoC (System On Chip), (eg: iMx6), which part is ARM
The definition of the CPU core(s) and their interfaces.
... and which is Freescale?
The physical implementation, including the design of any peripheral logic included on the chip.
Who did the integration?
Freescale, of course.
When I was involved in a chip design project which involved integrating an ARM, what we got was netlist Verilog. That is, a complete list of the gates and connections that make up the chip, but not in a higher-level form suitable for easy modification.
We then did our own placement and routing. This is usually necessary on each project as the shape of the chip area allocated to ARM will be different.
I believe multiple levels of license are available so you could buy a placed core in a standard shape already to save time.
(Placed netlists are exactly as they sound: a list of gates and their locations.)