Type vs Subtype and down vs to for Integers in VHDL

As you correctly say, a type is the base for subtypes; without type there is no subtype. However, subtypes are only safer in simulation; in real hardware, there are no boundary checks etc...

The standard library of VHDL defines a number of base types for you to build upon, like std_logic, std_ulogic, integer, character, std_logic_vector (unconstrained) and so on. Your own definitions like std_logic_vector(7 downto 0) create a subtype indirectly (or directly if you define and name your subtypes explicitly)

When you are looking at your own enumerations, e.g., when describing the states of a state machine, you need a type:

type tState is (IDLE, DO_SOMETHING, DONE);

I am not sure about the downto and to for the integers, it seems useless, but VHDL simply does not have another mechanism to define a range, and this mechanism allows both to and downto