Transistor layout for AOI gate

It's been a few years since I last did this kind of thing, so I thought I'd try to figure it out.

Here's the transistor diagram:

Here's the transistor diagram with the intermediate nodes labeled 1-4, and with the Euler path drawn in for both the PUN and PDN:

Here's the stick layout:

NO you're not crazy. According the schematic the only NMOS that should be connected to node "g" is one of the S/D's of "e".

Also, the NMOS active cannot be one piece as drawn and there need only be one ground connection.