Should there be any PCB ground plane under a 16 MHz oscillator?

Choosing ground cutouts on the basis of the signal's speed is only part of the story. The oscillator, and the 'high speed signals' your link talks about, are different situations.

The oscillator is recommended to use a specific circuit layout. This is a very small circuit. Follow the data sheet. An adjacent ground plane would introduce much C to ground. It's likely that the oscillator requires certain ratios of capacitance, and maximum capacitance to function properly, hence their recommendation. At the frequencies involved, for the line lengths shown, it all works, don't sweat it, just follow the data sheet. The 'to minimise parasitics' statement confirms that it's the excess capacitance that they are concerned about. Even if it does not stop oscillation, excess C will increase power consumption, which could be an issue on lower power designs.

'High speed signals' crossing a ground plane from one IC to another should have a well-defined return current path close by. The simplest way to do this is with an unbroken ground plane underneath. There are other methods, if you know what you're doing, but the unbroken ground plane is easy to do and always works. If you introduce breaks or cutouts in the ground plane, then this disrupts the return current flow, which can cause all sorts of problems which can be quite difficult to diagnose.

It is important that when you've cleared a patch of ground plane under your oscillator that you don't then route a different high speed signal across that area, both for problems with that signal's integrity, and potential problems of interference to/from your oscillator.

AFAIK general requirements for any passive XTAL circuit are same: XTAL branch must be isolated from the rest as much as possible since it is critical to avoid parasitics. Usually these are:

  • Components must be placed close as possible to IC, with short traces
  • No high speed traces passing nearby or under
  • Avoid crosstalk / coupling between traces
  • GND part must be isolated from "general" GND. If plane is used, it must be separated by gap (even from "general" GND plane)
  • Sometimes guard ring around is recommended - GND path with vias (check STM AN2867 for example)

Regarding various techniques, I think it is better to figure out why (requirements) and then decide what fits and what is not.

Given $$Tjitter = Vnoise / SlewRate$$ and $$SlewRate = 2*pi*16MHz*1volt = 100 volts/uS$$ you need to identify the tolerable Tjitter and be realistic about the dB/dT (change in magnetic interference near the XTAL/Cpi1/Cpi2/ MCUGND/MCUVDD/XTALin/XTALout).

Suppose your PCB has SwitchingReg with 100MHz discontinuous ringing of amplitude 0.1 amps, 1cm from the XTAL/Cpi. 100MHz may be seriously attenuated by SkinDepth, depending on direction of arrival at 1cm by 1cm XTAL/Xpi area.

Using $$Vinduce = MU0 * MUr * Area / (2 *pi * distance) * dI/dT$$ the induced $$Vnoise = 2e-7 * 1cm * 1cm / 1cm * (0.1 * 628e+6)$$

Vnoise is 2e-7 * 0.01 * 63e+6 = 126 e-7-2+6 = 126e-3 = 0.126 volts.

The resultant XTAL Jitter, out of the onchip sin-to-square circuit is as before $$Tj = Vnoise/SlewRate$$ = 0.126 volts/10^+8volt/sec = 10 nanoseconds * 0.126 = 1.26 nanoseconds.

Can your system tolerate 1.26 nanoseconds of jitter, caused by the nearby SwitchReg upsetting the XTAL voltages?

At 16MHz, period 66ns, the 1.3 ns jitter is 2%.