Rising edge pulse detector from logic gates

You may implement this digital design for detecting rising edge.

^{simulate this circuit – Schematic created using CircuitLab}

The output will go high as soon as a rising edge is detected on the D input. The output is cleared on the next rising clock edge.

May be the delay generated by three not gates is less than the set up time. So you might want to check with some more odd number of not gates and this also explains why your circuit worked with an inductor