Fast bidirectional 3.3 to 5V level shifter

I am slightly skeptical on your architecture. I used ALVC256 chip for the 3V3-5V conversions, and even with this would-be-correct architecture there're several issues which, at some circumstances, may make device malfunction.

Consider the following:

• 50 MHz is 20 ns cycle, SRAM you are going to use is 15 ns read/write cycle. You have slack of only 5 ns to ensure that buses (address and data) are stable and select proper memory cell for access;
• Mismatching impedance will cause spikes and false positives at the SRAM side, killing your 5 ns slack and potentially accessing (reading/writing) wrong data. This may require very fine tuning to work properly under all conditions (e.g. temperature, power source condition).

If you want well working device, then

• Get 3V3 SRAM, and connect it to the FPGA without any converters using series resistors (which you can change to tune for impedance);
• OR relax frequency conditions down to, let's say, 20 MHz (50 ns cycle).