Clock Dividers with Clock Domain Crossing

Depends on your vendor

On most modern FPGA's of the two biggest vendors, your first assumption is correct and you won't need synchronization registers for the CDC if your clock divider is written correctly. The synthesis tools will take care of everything.

Synthesis tools by smaller vendors don't always take into account the known phase relationship between the clocks, which might mean you do need a proper CDC. From experience I can say that the old Libero tools for at least the older RTAX and ProASIC lines allow you to specify synchronous clocks, but the specification just gets ignored and proper CDCs need to be added at the RTL level.

Yes, it's all one clock domain as far as synthesis is concerned. You can draw a circle around all three modules, and there's only on clock entering that circle. The fact that some of the logic inside that circle runs at 10 MHz is largely irrelevant.

Depending on how your implemented your ÷10 logic, you'll make things easier or harder for the synthesis to meet timing, because it's going to be doing everything based on the 10 ns period of the master clock. Using a PLL would be good in this sense, because it can effectively eliminate any delay between the two clocks. If you used a ripple counter, that would be the worst, because it creates the largest amount of skew between the clocks. A synchronous counter would create a low, but controlled amount of skew.