Are there any non-ideal side-effects of putting capacitors in parallel to increase capacitance?

Paralleling capacitors is fine electrically. That actually reduces the overall ESR and increases the ripple current capability, usually more so than a single capacitor of the desired value gets you. There is really no electrical downside to this.

The prominent non-ideal effects are cost and space.

Depending on the industry you are dealing with, dormant failure modes could be a consideration.

5off 100uF @ +-20% means you maximum spread of terminal capacitance is: 400uF --> 600uF. Sure what are the odds that all are at the maximum or at their minimum...

If one capacitor failed open-circuit (solder, mechanical etc...) the total span is 320uF --> 480uF. & the nominal range lies within this, dormant failure that is not quickly detectable during any production PAT's.

Parallel capacitors can actually introduce resonance at high frequencies, especially if they have different values. See this link for more information. Especially the plot on page 3.

This is actually a big problem when decoupling BGAs as you cannot get the capacitors as close as you would like, and you need to use different values.